To facilitate electrical connection of circuitry on active surfaces of semiconductor devices, conductive vias may be formed from an active surface extending into a substrate comprising a semiconductor material. Ends of the conductive vias may be exposed at an opposing backside surface of the substrate. Such vias are commonly referred to as “Through-Silicon Vias” or “Through-Substrate Vias” (TSVs). Each conductive via may be isolated (electrically and physically) from the substrate with a dielectric layer having a thickness of between about 50 nm and about 1,000 nm. Such a dielectric layer may also be referred to as a “spacer layer” or a “liner.” After the spacer-layer-encapsulated pillars of the conductive vias have been revealed by selectively removing material from the backside surface of the substrate, the backside surface of the substrate may be protected by depositing a barrier layer (e.g., of silicon nitride or silicon carbide) to prevent from diffusion of other materials (e.g., copper) into the substrate, forming electrical shorts between the conductive vias and the substrate. In addition, an oxide passivation layer may be deposited over the barrier layer to provide additional protection to the backside surface of the substrate and the barrier layer itself, as well as to isolate the conductive vias from one another. Thus, the chances of the metal materials contaminating the substrate, shorts forming between the conductive vias, and shorts forming between the conductive vias and the substrate may be significantly reduced. FIGS. 1A through 1E depict a conventional process for exposing the conductive material of a TSV in preparation for electrical connection.
With reference to FIG. 1A, a semiconductor device 100 in an intermediate state of fabrication is shown. The semiconductor device 100 comprises a thinned substrate 102 of semiconductor material such as, for example, a semiconductor wafer after backside grinding. The thinned substrate 102 is attached to a carrier substrate 104 using a temporary adhesive 106 for structural support during processing and handling. The grinding process may be relatively rapid, though imprecise, which may leave significant thickness variation in the remaining material of the substrate 102. Consequently, the ends of some conductive vias 108 may be much farther from a backside surface 112 of the substrate 102 than ends of other conductive vias 108. A conductive via 108 encapsulated in a spacer oxide shell 109 extends from an active surface 110 of the substrate 102 toward an opposing backside surface 112 of the substrate 102. As shown in FIG. 1B, a portion of the semiconductor material of the substrate 102 may be removed from the backside surface 112 by, for example, a dry etch process to expose the conductive via 108 at the backside surface 112. The material removal process may be selective, such that the spacer oxide shell 109 remains intact, reducing the risk of metal contamination to the exposed substrate 102. Referring to FIG. 1C, a barrier material 114, which may comprise silicon nitride (e.g., Si3N4), may be deposited over the backside surface 112 and the exposed portion of the conductive via 108, including the associated spacer oxide shell 109, using a conformal deposition process, such as, for example, a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. “Conformal deposition processes,” as used herein, include all deposition processes that are capable of depositing materials to all exposed surfaces of a structure, regardless of orientation, such that the topography of the resulting structure generally resembles the topography the surfaces exhibited prior to deposition. As shown in FIG. 1D, an isolation material 116, which may comprise silicon oxide (e.g., SiO2 or SiO), may be deposited over the barrier material 114 on a side opposing the substrate 102 using, for example, a conformal deposition process.
Referring to FIG. 1E, a portion of the isolation material 116, the barrier material 114, the spacer oxide shell 109, and the conductive via 108 may be removed to render a bottom surface 118 of the semiconductor device 100 substantially planar and expose an end of the conductive via 108 for electrical connection. For example, an abrasive planarization process, such as chemical-mechanical planarization (CMP) process, may be employed. The CMP process may stop before all of the isolation material 116 has been removed. The resulting semiconductor device 100 may include the barrier material 114 extending laterally over the backside surface 112 of the substrate 102 and longitudinally around a periphery of the conductive via 108. The isolation material 116 may extend laterally over the barrier material 114 and terminate at a portion of the barrier material 114 that extends longitudinally to cover a lateral exterior surface of the spacer oxide shell 109 surrounding the conductive via 108.
Conductive vias 108 exposed using the process described in connection with FIGS. 1A through 1E require deposition of a relatively thick layer of isolation material 116 (see FIG. 1D) to ensure all the conductive vias 108 are covered because the protruding height of individual vias 108 may vary significantly across an entire wafer. In addition, there is no clear indicator for when removal of the isolation material 116 and the barrier material 114 (see FIG. 1E) should stop. Insufficient removal means that some conductive vias 108 may not be exposed properly. Too much removal, especially by a mechanical process, such as CMP, may cause the conductive vias 102 to bend or otherwise deform, or even collapse due to applied shear force, compromising the connectivity of the semiconductor device 100, or may expose the substrate 102 to contamination by consuming all of the barrier material 114.